Search results for "Hardware architecture"
showing 10 items of 120 documents
Identification of parameters and harmonic losses of a deep-bar induction motor
2017
High frequency harmonics from a frequency converter causes additional losses in a deep-bar induction motor. The harmonics have their own amplitude and phase with respect to the fundamental signal, but the harmonic loss is only dependent on the amplitude of harmonics. A deep-bar induction motor can be modelled by a triple-cage circuit to take skin effect into account. The triple cage circuit having many parameters could be estimated from a small-signal model of the machine by using Differential Evolution. The correctly estimated parameters make the triple-cage circuit valid in a wide range of frequencies. However, the triple-cage circuit is very complicated which makes it difficult to model …
Learning automata based energy-efficient AI hardware design for IoT applications
2020
Energy efficiency continues to be the core design challenge for artificial intelligence (AI) hardware designers. In this paper, we propose a new AI hardware architecture targeting Internet of Things applications. The architecture is founded on the principle of learning automata, defined using propositional logic. The logic-based underpinning enables low-energy footprints as well as high learning accuracy during training and inference, which are crucial requirements for efficient AI with long operating life. We present the first insights into this new architecture in the form of a custom-designed integrated circuit for pervasive applications. Fundamental to this circuit is systematic encodin…
An FPGA-Based Adaptive Fuzzy Coprocessor
2005
The architecture of a general purpose fuzzy logic coprocessor and its implementation on an FPGA based System on Chip is described. Thanks to its ability to support a fast dynamic reconfiguration of all its parameters, it is suitable for implementing adaptive fuzzy logic algorithms, or for the execution of different fuzzy algorithms in a time sharing fashion. The high throughput obtained using a pipelined structure and the efficient data organization allows significant increase of the computational capabilities strongly desired in applications with hard real-time constraints.
Architecture of a digital PFM controller for IC implementation
2006
This paper presents a digital controller architecture oriented to IC implementation. The classical digital pulse width modulator (D-PWM), using digital analog converter (DAC), is replaced with a Sigma-Delta (/spl Sigma//spl Delta/) modulator based on pulse frequency modulator (PFM) technique. Results of an investigation from a prototype for DC-DC converter, in terms of simulated and experimental performances, are reported, together with harmonic frequency investigation. The control function design is implemented on a field programmable gate array (FPGA). As a consequence of good agreement between simulated and experimental results, the proposed architecture realizes a digital control loop w…
Coherence resonance in Bonhoeffer-Van der Pol circuit
2009
International audience; A nonlinear electronic circuit simulating the neuronal activity in a noisy environment is proposed. This electronic circuit is exactly ruled by the set of Bonhoeffer-Van Der Pol equations and is excited with a Gaussian noise. Without external deterministic stimuli, it is shown that the circuit exhibits the so-called 'coherence resonance' phenomenon.
On Brauer’s Height Zero Conjecture
2014
In this paper, the unproven half of Richard Brauer’s Height Zero Conjecture is reduced to a question on simple groups.
Circuit Lower Bounds via Ehrenfeucht-Fraisse Games
2006
In this paper we prove that the class of functions expressible by first order formulas with only two variables coincides with the class of functions computable by AC/sup 0/ circuits with a linear number of gates. We then investigate the feasibility of using Ehrenfeucht-Fraisse games to prove lower bounds for that class of circuits, as well as for general AC/sup 0/ circuits.
Improving computation efficiency using input and architecture features for a virtual screening application
2023
Virtual screening is an early stage of the drug discovery process that selects the most promising candidates. In the urgent computing scenario it is critical to find a solution in a short time frame. In this paper, we focus on a real-world virtual screening application to evaluate out-of-kernel optimizations, that consider input and architecture features to improve the computation efficiency on GPU. Experiment results on a modern supercomputer node show that we can almost double the performance. Moreover, we implemented the optimization using SYCL and it provides a consistent benefit with the CUDA optimization. A virtual screening campaign can use this gain in performance to increase the nu…
Shuttling-Based Trapped-Ion Quantum Information Processing
2020
Moving trapped-ion qubits in a microstructured array of radiofrequency traps offers a route toward realizing scalable quantum processing nodes. Establishing such nodes, providing sufficient functionality to represent a building block for emerging quantum technologies, e.g., a quantum computer or quantum repeater, remains a formidable technological challenge. In this review, the authors present a holistic view on such an architecture, including the relevant components, their characterization, and their impact on the overall system performance. The authors present a hardware architecture based on a uniform linear segmented multilayer trap, controlled by a custom-made fast multichannel arbitra…
Continuous Monitoring of Parasitic Elements in Boost Converter Circuit
2021
The given paper explains the necessity of condition monitoring for DC/DC boost converter circuit. Further, an analytical model of circuit parasitic estimation is presented based on measured quantities in the circuit. The implementation of continuous estimation of circuit parasitic elements is analytically explained and verified by simulations and experimental results. Obtained results are acceptable for condition monitoring.